Embodiments of the present invention relate to a semiconductor device including a buried bit line, and more particularly to a semiconductor device for preventing a bridge between contiguous storage node contacts (SNCs) and a method for manufacturing the same.
Although the demand of implementing a high-capacity dynamic random access memory (DRAM) is rapidly increasing, simply increasing chip size to accommodate additional memory has limitations.
The larger the chip size, the less the number of chips on each wafer, resulting in a reduction of productivity. Therefore, in recent times, many people and developers are conducting intensive research into a method for reducing a cell region by varying a cell layout to form a large number of memory cells on one wafer. By such efforts, a semiconductor layout is rapidly changing from an 8F2 structure to a 6F2 structure.
However, the 6F2 structure uses a storage node contact (SNC) space that is smaller than the 8F2 structure. Therefore, in order to form the 6F2 layout, a storage node contact (SNC) hole is formed and a lateral surface of a lower part of the SNC hole is additionally etched, so that a contact region between a storage node and an active region is increased in size.
However, when an insulation film located at a lower part of a bit line is excessively etched during the above additional etching process, a bridge may unexpectedly occur between SNCs to be formed in a subsequent process.